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Translators | MC100EPT24

Translator, LVTTL / LVCMOS to Differential LVECL

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Overview

The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a -3.3V, +3.3V and ground are required. The small outline 8-lead SOIC package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium.

  • Level Translator

  • 350ps Typical Propagation Delay
  • Maximum Frequency > 1.0GHz
  • The 100 Series Contains Temperature Compensation
  • Operating Range: VCC= 3.0 V to 3.6 V; VEE= -3.6 V to -3.0 V; GND = 0 V
  • PNP LVTTL Inputs for Minimal Loading
  • Q Output will default HIGH with inputs open
  • Pb-Free Packages are Available

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Reference Price

MC100EPT24DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-8

948R-02

3

260

TUBE

100

Y

1

TTL

ECL

3.3

1000

0.53

170

Price N/A

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MC100EPT24MNR4G

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Active

CAD Model

Pb

A

H

P

DFN-8

506AA

1

260

REEL

1000

Y

1

TTL

ECL

3.3

1000

0.53

170

Price N/A

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Reliability Data

Die Related Summary Data

Device: MC100EPT24DTG

Equivalent to wafer fab process: MOSAIC

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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