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Translator, Triple PECL Input to LVPECL Output

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Overview

The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals.

To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply, the LVCC supply is to be connected to the 3.3 V LVPECL supply, and Ground is connected to the system ground plane. Both the VCC and LVCC should be bypassed to ground with 0.01 F capacitors.

The PECL VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

  • 500ps Propagation Delays
  • 5V and 3.3V Supplies Required
  • ESD Protection: >2 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • LVPECL Operating Range: LVCC = 3.0 V to 3.8 V
  • PECL Operating Range: VCC = 4.5 V to 5.5 V
  • Internal Input Pulldown Resistors
  • Q Output will Default LOW with Inputs Open or < GND+1.3 V
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 247 devices
  • Pb-Free Packages are Available

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Reference Price

MC100LVEL92DWG

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Active

CAD Model

Pb

A

H

P

SOIC-20W

3

260

TUBE

38

Y

3

ECL

ECL

3.3

600

0.61

530

Price N/A

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MC100LVEL92DWR2G

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Active

CAD Model

Pb

A

H

P

SOIC-20W

3

260

REEL

1000

Y

3

ECL

ECL

3.3

600

0.61

530

Price N/A

More Details

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