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Latches & Registers | 74LVX373

Low Voltage Octal Transparent Latch with 3-STATE Outputs

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Overview

The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in the high impedance state. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.

  • This product is general usage and suitable for many different applications.

  • Input voltage translation from 5V to 3V
  • Ideal for low power/low noise 3.3V applications
  • Guaranteed simultaneous switching noise level and dynamic threshold performance

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VCC Min (V)

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74LVX373M

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Obsolete

CAD Model

Pb

A

H

P

SOIC-20W

751BJ

1

260

TUBE

1080

N

Latch

8

2

3.6

13.2

4

Price N/A

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74LVX373MTCX

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Active

CAD Model

Pb

A

H

P

TSSOP-20

948AQ

1

260

REEL

2500

N

Latch

8

2

3.6

13.2

4

$0.3244

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Reliability Data

Die Related Summary Data

Device: 74LVX373M

Equivalent to wafer fab process: CMOS STD

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

CMOS STD

3

3597164517

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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