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AMD Artix US+

Non-hardware verified power tree for AMD Artix US+ FPGA designs.

Block Diagram (AU10P/15P)

Please refer to the "Design Tools, Software and Chat AI" section of our Terms of Use.

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Synchronous buck regulator EN and PG. VIN from 2.3V to 5.5V, Vout from 0.3V to 2V, up to 3A load. 1.36x0.432mm WLCSP12.

Available Soon

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500mA LDO, 1.8V VOUT, with Enable / Power Good. WDFNW6_2x2mm.

Spice Model

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Synchronous buck regulator w/ Enable / Power Good. VIN from 2.9V to 5.5V up to 6A load. VOUT from 0.6V to 0.84 X VIN3x3mm QFN16.

Webdesigner+

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Source/sink Double Data Rate (DDR1, 2, 3) 3A termination regulator.

Available Soon

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1A LDO, 1.2V VOUT, with Enable / Power Good WDFNW6_2x2mm.

Spice Model

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Block Diagram (AU20P/25P)

Please refer to the "Design Tools, Software and Chat AI" section of our Terms of Use.

Part Number

Descripton

Tools

Product Family

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Synchronous buck regulator EN and PG. VIN from 2.3V to 5.5V, Vout from 0.3V to 2V, up to 3A load. 1.36x0.432mm WLCSP12.

Available Soon

More Details

500mA LDO, 1.8V VOUT, with Enable / Power Good. WDFNW6_2x2mm.

Spice Model

More Details

Synchronous buck regulator w/ Enable / Power Good. VIN from 2.9V to 5.5V up to 6A load. VOUT from 0.6V to 0.84 X VIN3x3mm QFN16.

Webdesigner+

More Details

Source/sink Double Data Rate (DDR1, 2, 3) 3A termination regulator.

Available Soon

More Details

1A LDO, 1.2V VOUT, with Enable / Power Good WDFNW6_2x2mm.

Spice Model

More Details

1A LDO, 1.2V VOUT, with Enable / Power Good WDFNW6_2x2mm.

Spice Model

More Details

Show More