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1.8 V / 2.5 V, 10 GHz ÷·2 Clock Divider with CML Outputs

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Overview

The NB7V32M is a differential divide-by-2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V32M produces a divide-by-2 output copy of an input Clock operating up to 10GHz with minimal jitter. The Reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the Reset allows for the synchronization of multiple NB7V32M's in a system. The 16mA differential CML output provides matching internal 50-ohm termination which guarantees 400mV output swing when externally receiver terminated with 50-ohm to VCC. The NB7V32M is the 1.8V/2.5V version of the NB7L32M 2.5V/3.3V and is offered in a low profile 3mm x 3mm 16-pin QFN package.

  • Test & Measurement, ATE

  • Instumentation, Networking

  • Maximum Input Clock Frequency > 10 GHz, typical
  • Random Clock Jitter < 0.8ps RMS
  • 30ps Typical Rise and Fall Times
  • Differential CML Outputs, 400mV peak-to-peak, typical
  • -40C to +85C Ambient Operating Temperature

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MSL Type

MSL Temp (°C)

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Type

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

NB7V32MMNTXG

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CAD Model

Pb

A

H

P

QFN-16

1

260

REEL

3000

N

Divider

LVDS

CML

2.5

10000

0.2

60

Price N/A

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