Name: 3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset
Brand: 3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset
SKU: MC10EP451

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3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

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Overview

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < V_EE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.

The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.

The 100 Series contains temperature compensation.

High Performance Logic for test systems

450 ps Typical Propagation Delay
Maximum Frequency > 3.0 GHz Typical
Asynchronous Master Reset
20 ps Skew Within Device, 35 ps Skew Device-To-Device
PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V with V_EE = 0 V
NECL Mode Operating Range: V_CC = 0 V with V_EE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available

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Reference Price

MC10EP451FAG

Active

LQFP-32

561AB

260

JTRAY

250

ECL

0.2

0.45

0.08

0.15

250

3000

Price N/A

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MOSAIC

476668904

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Flip-Flops, Latches & Registers | MC10EP451

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