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Flip-Flops, Latches & Registers | NB4L52

2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

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Overview

The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.

  • High Performance Logic for ATE and Networking

  • Maximum Input Clock Frequency > 4 GHz Typical
  • 330 ps Typical Propagation Delay
  • 145 ps Typical Rise and Fall Times
  • Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
  • Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V

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Reference Price

NB4L52MNG

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Active

CAD Model

Pb

A

H

P

QFN-16

485G-01

1

260

TUBE

123

Y

D-Type

1

LVDS

ECL

5

1

0.4

0.1

0.05

0.4

190

4000

Price N/A

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NB4L52MNR2G

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Active

CAD Model

Pb

A

H

P

QFN-16

485G-01

1

260

REEL

3000

Y

D-Type

1

LVDS

ECL

5

1

0.4

0.1

0.05

0.4

190

4000

Price N/A

More Details

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Reliability Data

Die Related Summary Data

Device: NB4L52MNG

Equivalent to wafer fab process: MOSAIC

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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